The present invention is related to devices and circuits for synthesizing a clock, and more particularly to on-chip approaches for synthesizing a clock signal.
Clock synthesizing is a process whereby a clock signal of a particular frequency and phase is generated based on a frequency reference. Clock synthesizing may be done using a phase lock loop circuit as has become common in many circuit implementations. A typical phase lock loop application utilizes off-chip varactor diode based tuning elements that require large voltage swings to effect a large tuning range. In some implementations, an off-chip power source providing a potential much greater than that provided to the semiconductor device on which the phase lock loop circuit is implemented is used to facilitate the desired large voltage swings.
An example of one such implementation is depicted in FIG. 1 where a semiconductor device 100 includes a phase lock loop circuit 110 providing a clock signal 130. Clock signal 130 may be used to synchronize one or more functions implemented on semiconductor device 100. Semiconductor device 100 is powered by a low voltage power source 120. Phase lock loop circuit 110 includes an off-chip oscillator circuit 140 outlined by dashed lines and powered by a high voltage power source 150. Off-chip oscillator circuit 140 includes a capacitor 142, a capacitor 146, and a resistor 144. In one particular implementation, high voltage power source 150 is approximately thirty volts, while low voltage power source 120 is approximately three volts.
While the circuit of FIG. 1 provides an ability to synthesize a desired clock signal, the circuit requires an off-chip power source in addition to the power source used to drive semiconductor device 100. Such an off-chip high voltage power source is costly both in terms of board area and component cost.
Hence, for at least the aforementioned reasons, there exists a need in the art for approaches for synthesizing a clock signal.